A typical processing system with video/graphics display capability includes a central processing unit (CPU), a display controller coupled with the CPU by a system bus, a system memory also coupled to the system bus, a frame buffer coupled to the display controller by a local bus, peripheral circuitry (e.g., clock drivers and signal converters), display driver circuitry, and a display unit. The CPU generally provides overall system control and, in response to user commands and program instructions retrieved from the system memory, controls the contents of graphics images to be displayed on the display unit. The display controller, which may for example be a video graphics architecture (VGA) controller, generally interfaces the CPU and the display driver circuitry, exchanges graphics and/or video data with the frame buffer during data processing and display refresh operations, controls frame buffer memory operations, and performs additional processing on the subject graphics or video data, such as color expansion. The display driver circuitry converts digital data received from the display controller into the analog levels required by the display unit to generate graphics/video display images. The display unit may be any type of device which presents images to the user conveying the information represented by the graphics/video data being processed.
The frame buffer, which is typically constructed from dynamic random access memory devices (DRAMs), stores words of graphics or video data defining the color/gray-shade of each pixel of an entire display frame during processing operations such as filtering or drawing images. During display refresh, this "pixel data" is retrieved out of the frame buffer by the display controller pixel by pixel as the corresponding pixels on the display screen are refreshed. Thus, the size of the frame buffer directly corresponds to the number of pixels in each display frame and the number of bits (Bytes) in each word used to define each pixel. The size and performance of frame buffer is dictated by a number of factors such as, the number of monitor pixels, the monitor DOT clock rate, display refresh, data read/write frequency, and memory bandwidth, to name only a few.
The frame buffer memory bandwidth is typically constrained by the speed of the memory devices available. For example, a pair of the fastest presently available 256k.times.16 DRAMs operating in the page mode can, without interleaving, only provide display refresh data to the display controller at a maximum of rate of 80 to 100 megabytes/second across a 32-bit interface. This limited range accounts not only for the limits on device access time but also for the fact that the frame buffer is simultaneously being burdened with other tasks such as cell refresh, off-screen memory accesses and writes to the on-screen memory. While the available bandwidth may be sufficient for systems driving displays with lower resolutions and/or lower bit depths, it will not support state of the art high resolution/high bit depth displays. For instance, a 1280 by 1024 pixel display with a pixel color depth of 8 bits/pixel being refreshed at 72 hertz requires data from the frame buffer (through the controller) at a rate of at least 130 megabytes/sec.
Interleaving of the DRAMs (or the random ports of VRAMs when VRAMs are used) of the frame buffer is a memory control/partitioning scheme used in some display systems to improve bandwidth. In a two bank interleaving scheme, the frame buffer is divided into odd and even banks from which data is alternately retrieved. Depending on the speed data is retrieved from each bank and the speed at which the controller switches between banks, substantial increases in the rate the controller receives data from the memory can be achieved. For example, assume that each bank outputs data at a rate of 40 MHz and the display controller switches between banks at a rate of 80 Mhz, the controller receives a stream of words from the frame buffer at approximately 80 MHz. For a given word width, the bandwidth of the memory is essentially doubled. Interleaving can be similarly extended to memories partitioned more than two banks.
While interleaving provides increased bandwidth, the complexity of implementing interleaving have limited its application to high end systems. In particular, the timing and control of the memory becomes a more precise and complicated task for the controller. Not only must the controller generate additional bank enable signals for switching between banks, but it must also generate the conventional DRAM control signals (RAS, CAS, OE) necessary to retrieve data from each bank at the appropriate times. In sum, for systems employing interleaving, enhanced controller hardware and/or software is typically required.
Thus, the need has arisen for circuits, systems and methods for constructing and controlling a memory. Such circuits, systems and methods should allow for the high speed access of data from memory without resort to complex timing schemes required by conventional interleaving techniques. Further, such circuits, systems and methods should be particularly applicable to the control and construction of graphic/video frame buffers.